Recent developments have combined a coder-decoder (CODEC) and digital signal processor (DSP) on a common chip. Currently, microprocessor architectures implement either a single CODEC or none at all. Due to developments in multi-channel signal processing architectures, at least two microprocessors are needed, each independently having a CODEC and a phase-locked loop (PLL). However, when multiple microprocessors are used, their respective CODECs are generally not synchronized.
Because the acquisition times of internal PLL clock generators vary between microprocessors, the exact synchronization times cannot be controlled. All events between the two microprocessors are not co-incident due to this lack of synchronization, thus causing the CODECs to obtain their samples at slightly different times. However, there are many applications which utilize multiple microprocessors where the data or signal samples need to be obtained at precisely the same instants of time.
One such application is in wireless data communications in the field of diversity reception where two or more independent receivers are employed. Each receiver contains various components including a microprocessor (e.g., a DSP) and a CODEC within each microprocessor. For coherent signal combination the signals from each microprocessor must be obtained at precisely the same instants of time, or substantial processing delays must be introduced to compensate.
A solution for obtaining synchronized sampling with multiple CODECs is to drive them with a common clock. A high frequency clock is fed into both microprocessors and, in turn, the PLLs are bypassed. Unfortunately, even when the microprocessors are driven by a common clock, the CODECs may still not be synchronized. This is due to the fact that a portion of the feedback path of the PLL is implemented utilizing analog components, and due to the variability of these analog components, the lock time of such PLLs cannot be as precisely obtained as is required for coherent signal combination.
It is well known in electrical design that it takes a variable amount of time for the PLL to stabilize, due to the variability of the analog components, before accurate sampling of a signal can be established. This variable amount of time is a function of the characteristics of the materials from which the components are manufactured, as well as the conditions, such as minimum and maximum operating temperature, under which the components may operate. Component manufacturers publish these characteristics as part of the specifications for the components which they sell.
A high frequency clock cannot be fed into both microprocessors and, in turn, bypass the internal PLLs because of the side effects of electromagnetic interference. The electromagnetic interference is due to the high frequency coupling which adversely impacts the adjacent analog circuitry.
A hardware solution to the same problem involves extensive shielding and significant layout changes. However, the hardware solution is discounted due to significant increase in cost.
Thus, a need exists to bring sampling instants of a first CODEC of a first microprocessor into synchronization with sampling instants of a second CODEC of a second microprocessor to allow for coherent signal combination without major modifications to the hardware.